In recent years, designing printed circuit boards (PCBs) has become increasingly complex. Operating frequencies have increased, rise-time of signals has shortened, board sizes have become increasingly compact and interfaces have become increasingly critical. Typically, High Speed PCB design requires good routing practices to reduce the effect of signal integrity parameters such as reflection, crosstalk, simultaneous switching noise (SSN) and electromagnetic interference (EMI). These parameters, which decrease the efficiency of device employing such PCBs over a period of time, are minimised by imposing particular constraints on the respective PCB design.
Signal Integrity Engineers often use tools to force routing rules/constraints on critical signals of some high-speed interfaces. The tool ensures that transmitted signal do not violate design rules required for optimum functioning of the PCB. Using the constraints tool to, based on an existing design file (Rev 0), create a new design file (Rev 1) is often associated with a change in attributes attached to the original file, such as net names, reference designators (refdes) and extended electrical nets. The constraints of signals with altered net-names or the refdes are redefined manually for the new design.
For example, a typical processor—SDRAM interface includes around 32 data signals, 8 data strobe & 8 mask signals, 12-14 address lines, clocks & control signals, making it a total of around 70 signals. When there is a change in net-names of these signals, for example, the data signals are changed from sdram_data0 to sdram data—0, the Address signals are changed from sdram_addr0 to sdram_addr—0 etc. Thus, if a new design is created, there would be a new netlist imported into the design. Even if there is no change in the net-logic or the topology, previously assigned constraints are removed and the constraints for the entire interface are deleted. The buses & constraints for each of the signals have to be re-created. This is a time consuming process, which substantially reduces the efficiency of the design process.